AW: Art's Studies
Arthurs leisure time
http://noobs-r-us.co.uk/attachment.php?attachmentid=1568&stc=1&d=1395596984
Arthurs leisure time
http://noobs-r-us.co.uk/attachment.php?attachmentid=1568&stc=1&d=1395596984
There will no hijacking this most serious thread with your inane noobs nonsense ! ! 
Art is coming over to the Dark Side of High Speed Digital Electronics ! muahahahaha and Yes we have Cookies !
There are 10 types of people in the world: Those who understand binary, and those who don't.
Art is coming over to the Dark Side of High Speed Digital Electronics ! muahahahaha and Yes we have Cookies !
There are 10 types of people in the world: Those who understand binary, and those who don't.
There will no hijacking this most serious thread with your inane noobs nonsense ! !
Art is coming over to the Dark Side of High Speed Digital Electronics ! muahahahaha and Yes we have Cookies !
There are 10 types of people in the world: Those who understand binary, and those who don't.
yea, indeed - exactly 10
lol
Mini, I would like to thank you for taking the time to help and support Art.
That’s very kind of you.
Art, you have never failed and with your sincere focus you never shall.
Wishing you the best of luck for your final exams.
May you pass with flying colours.
That’s very kind of you.
Art, you have never failed and with your sincere focus you never shall.
Wishing you the best of luck for your final exams.
May you pass with flying colours.
Mini, I would like to thank you for taking the time to help and support Art.
That’s very kind of you.
Art, you have never failed and with your sincere focus you never shall.
Wishing you the best of luck for your final exams.
May you pass with flying colours.
And may these colours be RGB in right proportion...
Thank you Manuela for your support - you made me blush now....
100% red
Mini, I would like to thank you for taking the time to help and support Art.
That’s very kind of you.
Art, you have never failed and with your sincere focus you never shall.
Wishing you the best of luck for your final exams.
May you pass with flying colours.
And may these colours be RGB in right proportion...
Thank you Manuela for your support - you made me blush now....
dont forget the alpha channel ^^ ! noooobie
Right back on track.....We'll have no Alpha bended RGB please Steffos....We are RGB Full scale men here 0 - 255. None of your RGB limited crap either 16 -235
had a talk with a designer today Art and they dont use the GUI when they use the tools, they tend to invoke compile, synthesis, map, place and route etc etc all by scripted batch files. Its easier to control under Version control SW and its easier to see what settings you are using.
Now hes asked one of the other designers in India who may know about the GUI end but I have done some reading up myself !
I will point you at this doc http://www.altera.com/literature/hb/qts/qts_qii5v3.pdf
Chapter 1 and Chapter 2 are pretty much enough to get you going on gatelevel post synthesis sims ! Chapter 1 is more about using Quartus and Native link...Chapter 2 is more about invoking everything from modelsim...read both chapters ! then read them again !
This doc is also pretty good -> http://cseweb.ucsd.edu/classes/fa10/cse140L/lab2/Lab2_tutorial_timinig_simulation.pdf .....little bit fluffy but ok for a high level of what we are tryign to do.
What you are trying to do is synthesis your design (and create a simulaiton model), then either by
1. using Quartus and NativeLink to pass the relevant commands into model sim
2. running the commands yourself in modeslsim
get a sim of the actual synthesised design.
If you have any updates or questions post away and we'll see where we go next. How did the design partionaning and pipelineing go btw ?
Another handy debug tool is the SystemTap logic analyser....its a logic anaylser you build into the design and then connect to it via JTAG when the FPGA is live, this is called Chipscope in Xilinx and I'm very familar with it....On the Altera I know it called SystemTap...Think of it as many channles of oscilliscope inside the FPGA as it runs in real time...Very powerfull tools but like anyting there is a bit to setting them up
had a talk with a designer today Art and they dont use the GUI when they use the tools, they tend to invoke compile, synthesis, map, place and route etc etc all by scripted batch files. Its easier to control under Version control SW and its easier to see what settings you are using.
Now hes asked one of the other designers in India who may know about the GUI end but I have done some reading up myself !
I will point you at this doc http://www.altera.com/literature/hb/qts/qts_qii5v3.pdf
Chapter 1 and Chapter 2 are pretty much enough to get you going on gatelevel post synthesis sims ! Chapter 1 is more about using Quartus and Native link...Chapter 2 is more about invoking everything from modelsim...read both chapters ! then read them again !
This doc is also pretty good -> http://cseweb.ucsd.edu/classes/fa10/cse140L/lab2/Lab2_tutorial_timinig_simulation.pdf .....little bit fluffy but ok for a high level of what we are tryign to do.
What you are trying to do is synthesis your design (and create a simulaiton model), then either by
1. using Quartus and NativeLink to pass the relevant commands into model sim
2. running the commands yourself in modeslsim
get a sim of the actual synthesised design.
If you have any updates or questions post away and we'll see where we go next. How did the design partionaning and pipelineing go btw ?
Another handy debug tool is the SystemTap logic analyser....its a logic anaylser you build into the design and then connect to it via JTAG when the FPGA is live, this is called Chipscope in Xilinx and I'm very familar with it....On the Altera I know it called SystemTap...Think of it as many channles of oscilliscope inside the FPGA as it runs in real time...Very powerfull tools but like anyting there is a bit to setting them up
Yeaa, SIGNALTAP! Was trying to deploy it, didn't succeed yet it's a bit touchy, needs woodoo techniques to make it work.
I've heard about scripting issue in modelsim, but i'm kind of a beginner, didn't try it yet, except of "vlib work, vmap work work, add wave *, add wave -r, force" lol you meant *.do files?
So far, breaking the design into smaller components has some positive effects, at least i can see right signals with correct timing (at last) but, it's a bit pain in the arse to integrate them together - the pipelining. When it was a single state machine - the logic was a bit easier.
I'm going to use those PDFs that you have sent me in my project for sure.
it's a bit touchy, needs woodoo techniques to make it work. I've heard about scripting issue in modelsim, but i'm kind of a beginner, didn't try it yet, except of "vlib work, vmap work work, add wave *, add wave -r, force" lol you meant *.do files?
So far, breaking the design into smaller components has some positive effects, at least i can see right signals with correct timing (at last) but, it's a bit pain in the arse to integrate them together - the pipelining. When it was a single state machine - the logic was a bit easier.
I'm going to use those PDFs that you have sent me in my project for sure.
Yeaa, SIGNALTAP! Was trying to deploy it, didn't succeed yet
[Mini] lol...its not that bad, well chipscope anyway...I'll have to read up on signaltap
I've heard about scripting issue in modelsim, but i'm kind of a beginner, didn't try it yet, except of "vlib work, vmap work work, add wave *, add wave -r, force" lol you meant *.do files?
[Mini] yep exactlely that.... .do files and batch files... basically the designers can from a command promt kick off a full build... compile, synthesis, palce route all the way to end bit file without using the GUI
So far, breaking the design into smaller components has some positive effects, at least i can see right signals with correct timing (at last) but, it's a bit pain in the arse to integrate them together - the pipelining. When it was a single state machine - the logic was a bit easier.
[Mini] the statemachine should be ok to keep as one whole block, its only the other blocks that you should break out. Do you have a block diagram of the design ?
I'm going to use those PDFs that you have sent me in my project for sure.
[Mini] Lol its all about the ammount of pages in a report not the content
My comments above ^^ [Mini]
lol im only a C++(+ Qt) and JS beginner muhahaha
I have a strong feeling, that i'm going to learn them too
lol
yea, I have a block diagram. I'm drawing them on a daily basis
tried the post synthesis simulation, the file you sent me yesterday - the design works fine again.
every HW should know some SW and other way round
im making dual studies ill start HW in this autumn ^^ for now i only do SW how you call it
full title in german is "Dualer Student für Fachinformatik im Fachgebiet Anwendungsentwicklung und Elektro und Informationstechnik "
absloute fuckin disaster this is ^^
AW: Re: Art's Studies
The real title in german is "Fachidiot, der den arbeitenden Leuten das Leben schwer macht und sie in den Wahnsinn treibt.
English bad translation: They called idiots, who make the poor workers a hard life and drive them crazy. :arg:
The real title in german is "Fachidiot, der den arbeitenden Leuten das Leben schwer macht und sie in den Wahnsinn treibt.
English bad translation: They called idiots, who make the poor workers a hard life and drive them crazy. :arg:
yea, I have a block diagram. I'm drawing them on a daily basis
tried the post synthesis simulation, the file you sent me yesterday - the design works fine again.
every HW should know some SW and other way round
im making dual studies ill start HW in this autumn ^^ for now i only do SW how you call it
full title in german is "Dualer Student für Fachinformatik im Fachgebiet Anwendungsentwicklung und Elektro und Informationstechnik "
can you say "Anwendungsentwicklung" 5 times and quicly?
lol cause, when i'm trying to read it, I forget the beginning of the word when i reach the middle