Art's Studies

[_MiNi_]

The block can support up to 4 input clocks Art, you dont need to use all 4

Look at the paramater in the decleration

parameter number_of_clocks = 4,

if you only need 1 clock input set this to 1

Likewise

In the ports
input wire [number_of_clocks-1:0] inclk

by you setting the number_of_clocks paramater = 1 then the input wire inclk is now only a single bit wide

 

[_MiNi_]

Opps sorry that was verilog ^^^^^

But the same applies for the VHDL

number_of_clocks:natural := 4;

&

inclk: in std_logic_vector(number_of_clocks-1 downto 0) :=
(others => '0');

by setting number_of_clocks = 1 then the std_logic_vector reduces to (1-1 down to 0) or (0 downto 0) which the compiler/synthesis tool will recognise as a single bit


If you wanted to be be Jonny Flash you could leave the number of input clocks as 4 and just tie 3 off to '0' and use one.


Say you want to only use inclk[0] :-

inclk(0) <= arts_CLK;
inclk(3 downto 1) <= (others => '0');

 

[Art_Br83]

arts_CLK is std_logic not std_logic_vector

i'll take a closer look tomorrow - have no mood right now

 

[_MiNi_]

yep but you can connect a std_logic to a single element of a bus

you may have to do sillyness though like declare arts_CLK as a 1 bit vector

 

[Art_Br83]

IT'S ALIVE!!! IT'S ALIVE!!! BIATCH!!! (almost)


[video=youtube_share;xos2MnVxe-c]http://youtu.be/xos2MnVxe-c[/video]

 

[_MiNi_]

*Happy Dance*

*Happy Dance*

NRU.....A battlefield Clan & NEW ! VHDL forums !

 

[Sweney]

my head hurts lol if u need lumber cut into shapes so u can build a house with them im your man

 

[Art_Br83]

The SCHEEIISSEEE enable signal was wanky - only one signal that was breaking the whole loop - and nothing worked. Until I made a dedicated slide switch for him, then a dedicated component... And here we go again dancing and screaming.

 

[Art_Br83]

Thank you Mini i've learned a few things in design tests

 

[Art_Br83]

from a closer examination of my design, i found one more FUCKUP (that I caused) - sampling and controlling faster process by a slower one and vice versa


need to make some clearings in the mess - because i broke it again

SCHEISSSE again!

 

[_MiNi_]

When you say slower process controling faster ones are these process clocked off the same clock or have you a slow clock and a fast clock ?

If both are clocked off the same clock then you will need to modify the state machines so that the process wil wait(just loop until READY) until the other process is ready, you'll need to bring a signal (READY)into the statemachine in order to progress. It all depends which way you are going, a faster clock is always going to be able to sample a signal off a slow clock, it will see it for multiple clock cycles....
A signal clocked from a fast clock however will need to be held long enough in order that setup-hold are respected in regard to the slow clk frequency.


If you have processes clocked from different clocks then its a similar approach but you are now bringing signals across clock domains and you need to resync the signals to the new clock.
Bringing a whole bus across a clock domain is tricker again.

Have a read of this article:
Understanding clock domain crossing issues | EE Times

 

[Art_Br83]

Yea, i have processes that clocked from different clocks, faster and slower one. The faster clock is sampling process, and the slower one is the execution process.

 

[_MiNi_]

When you sample the data with the fast clock you'll need to hold it and pass a ready signal to the slower process so that it knows its ok to read /accept the data !

 

[Art_Br83]

When you sample the data with the fast clock you'll need to hold it and pass a ready signal to the slower process so that it knows its ok to read /accept the data !

In order to do so, i have to clean my design a bit

 

[Art_Br83]

Miniii - Heeelp!!! F1!!! I have 1 more question. Pleaasseee - not a VHDL issue. All my digital design is working fine now thanx to signal_tap ,post_synthesis approaches and design rules that you suggested.

Now I have an unexpected problem in my analog design. I'm using an IC AD9225 - (A2D converter, from Analog Devices)

As you wrote previously, you're working with at Analog Devices. The IC refuses to function at all - despite all preparations and connecting it according to SPEC. The question is - perhaps you can find somewhere, somehow any application notes, testing procedures, or any other data regarding that A2D model?

 

[_MiNi_]

No problem at all Art, I'll ask around tomorrow. Before I was in the video group I was a test engineer in the ADC group for 2 years so if the part was done out of Ireland I might know some engineers that worked with AD9225.

But saying that let me ask a few questions to you.
Can you share your schematics of how you wired up the AD9225 ?

Now like the VHDL we are going to start small

Are the supply/gnd pins connected ? Have you used decoupling caps across the supplies ?
Are you using the internal bandgap reference or are you supplying your own ? If you are supplying an external reference, is it clean and noisefree ? What is the Vref for your application ?
Are you using a nice clean clock input ? Is it within freq spec for the part ?
How are you connecting to the ADC input ? Are you DC or AC coupled ? Are you using an opamp/buffer on the ADC inputs ?
Are you using single eneded or differential input ?
Have you seen any activity at all out of the part on the digital outputs ?
Have you tried inputting a 1khz sinewave ?
Did you connect caps to the CAPT CAPB pins ?

 

[Art_Br83]

LoL Mini, where have you been all my life? Thanks a lot for your help

ok, lets start the check list
Supply/GND pins - checked
Decoupling caps across supplies - everywhere, on +-VDDs 100nF (should i put on GNDs too?)
I'm using the INTERNAL reference of 1v for signal span 0 to 2v (CCD signal) - it's noisy.
Nice clean clock - it's nice but not so clean, since my board is not a nice PCB (i'm going to lower the clock today from 25MHz downto 8MHz)
Clock rate is within spec boundaries.
ADC input - single ended mode, DC coupled with op-amp buffer including matching resistors that recommended by spec. BUT, i was checking it with connecting its input to GND in order to see x"000" in digital outputs. FAILED - it showing all 111s, or some trash codes.
I started testing the OTR bit, according to spec testing methods - (out of range bit, that responds to VINa-VINb </>/= VREF ) it responds to slow raising SAW wave in the input - but not clearly.
Using saw wave for testing in order to find a proper reference level.
CAPT, CAPB pins connected. There is one cap of 10uF according to spec -but, for now it's only 2.2uF. Is it crucial?

 

[Art_Br83]

this is a brief description of my ADC configuration, that I ASSUME should work properly

 

[glenwilson]

what are u studying then exactly i'll start electro and communication techniques autumn of this year sounds very similiar

Electrical engineering, BSc - and yes Steffos, it's a part of my studies too. In addition I have digital hardware design. My question is related to that issue.

sounds better than the chemistry shite I did ..... you only have one chance at this and at times it will seem like complete bollocks but try to do it with the best effort you can. it may be the making of you in the future ...... or just quit it now and do something you enjoy ....maybe a fish farmer ? lol Isreali Koi ?

I had a chemistry set too. Found you could add most of the stuff to icing sugar and eat it. Which may explain some things like the extra head I grew!

 

[_MiNi_]

Hi Art,

Talked to the lads in ADC test group, AD9225 was not done in Limerick it was done out of Greensboro. (Boston)

Right lets go.
Supply/GND pins - checked
[MiNi] Good

Decoupling caps across supplies - everywhere, on +-VDDs 100nF (should i put on GNDs too?)
[MiNI] Decoupling cap get placed from the supply pin to GND. So the cap goes +VDD to GND or -VDD to GND. Be very carefull and never place caps across +VDD to -VDD unless specifically told to do do.

I'm using the INTERNAL reference of 1v for signal span 0 to 2v (CCD signal) - it's noisy.
[MiNi] Noisy reference will translate directly in LSB code changes at the digital output for a constant ADC input.

Nice clean clock - it's nice but not so clean, since my board is not a nice PCB (i'm going to lower the clock today from 25MHz downto 8MHz)
[MiNi] Bit of noise on the clock is ok...What I'm concered about is the clock rising and falling edge it should be monotonic.

Clock rate is within spec boundaries.
[MiNi] Sweet...for testing though I'd reduce this wayyyyyy down to try and rule out any issues.

ADC input - single ended mode, DC coupled with op-amp buffer including matching resistors that recommended by spec.
[MiNi] Cool


BUT, i was checking it with connecting its input to GND in order to see x"000" in digital outputs. FAILED - it showing all 111s, or some trash codes.
[MiNi] All 111's could be well correct. If you are not configured correctly in singled ended mode mode, you MUST have SENSE connected to VREF connected to VINB for 0 to 2V input. and 1V reference.

So if you are not configured correctly for 1V reference single ended remeber that this ADC is giving a straight min output code at -Vref all way to max code at +Vref.
-Vref input would give code 0000 0000 0000
+Vref input would give code 1111 1111 1111

Perfect 0V input with very clean reference would equate to code

1000 0000 0000

Allowing a few LSBs for noise and stuff....For 0V static dc input I'd expect to see codes from


1000 0000 0111 (0V + 3LSBs)
:
1000 0000 0000 (0V)
:
0111 1111 1000 (0V -3LSBs)

To check you are configured correctly, use a multimeter to check the volatge between pin VREF and GND. If you see 1V all is well


I started testing the OTR bit, according to spec testing methods - (out of range bit, that responds to VINa-VINb </>/= VREF ) it responds to slow raising SAW wave in the input - but not clearly.
[MiNi] Not clearly ? Are the codes not increasing nice and linearly ? Would point to noisy input or reference.
Is your Saw tooth increasing from 0V to 2V ? or is there some DC bias on it ?



Using saw wave for testing in order to find a proper reference level.
[MiNi] Nice idea

CAPT, CAPB pins connected. There is one cap of 10uF according to spec -but, for now it's only 2.2uF. Is it crucial?
[MiNi] Decoupling is always critical. Even down to the type of cap not just the values. Decoupling caps should be as close to the device pins as possible, with as short leads as possible, SMT are ideal but I reckon you are using leaded ? You are running a 25Mhz part here with a Vref of 1V and a resolution of 12bits.......Thats a LSB = 0.4 mV ! ! To put it in perspective only 2mV of noise it going to equate to 5 LSBs (bits) of code change !
Ideally this circuit would be on a multilayer PCB with a full GND layer. Is that an option for this project ?

I can see that Tants and ceramics are recommeded in the datasheet, try and get the specific type and value of decoupling recommend. Anytime you skimp on caps and layout its going to hit you in performance.

Remember that Vref pins needs decoupling caps too to GND, and also the CML pin needs a decoupling cap to GND.


Just to note too on your Input buffer.....is this buffer supplied from +V -V or is it +V and GND....
Check that what you getting out of the buffer and inputting to the ADC is 0V to 2V and not -V to +V.
if you are configured correctly for single ended and have a Vref of 1V and you are mistakenly inputting say -2V to +2V then anything under 0V will give 0000 0000 0000 output with OTR bit set.