GATED CLOCKs ! ! !
(Big boys stuff
)
Is your logic that big that you have such a massive clock tree and need to use gated clocks ??
Passing clocks through regualr logic (simple gates, mux etc) is usually avoided if at all possible as you could now have some parts of your design being clocked at T and other parts at T+1ns for example.
Look in the altera manuals for some specific Altera primitives for clock managment. It should have special clock buffers, muxes etc...the muxes should be able to garauntee glitchless switching, low latency, high frequency of operation that sort of stuff.
Actually a quick serach and I found this for you
http://www.altera.com/literature/ug/ug_altclock.pdf
It gives the VHDL instantation for the block too near the back and also which libraries you need to include to be able to access it.
component altclkctrl
generic (
clock_type:string := "AUTO";
intended_device_family:string := "unused";
ena_register_mode:string := "falling edge";
implement_in_les:string := "OFF";
number_of_clocks:natural := 4;
use_glitch_free_switch_over_implementation:string := "OFF";
width_clkselect:natural := 2;
lpm_hint:string := "UNUSED";
lpm_type:string := "altclkctrl"
);
port(
clkselect:in std_logic_vector(width_clkselect-1 downto 0) :=
(others => '0');
ena: in std_logic := '1';
inclk: in std_logic_vector(number_of_clocks-1 downto 0) :=
(others => '0');
outclk
ut std_logic
);
end component;
You'll need to include this lib in order to use the altclkctrl block
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
Have a read of the .pdf document and see if it can be configured to fit the need you have.
Nice little page too on clock multiplexers
TimeQuest Clock Multiplexer Examples
Its good to hear you are begining to see some differences between the RTL and post synthesis sims...At least if the post synth sims match what you see in real life on the fpga then you know if you fix it to work in sims then the real life design should be fixed now too