Art's Studies

Welcome to our Community
Wanting to join the rest of our members? Feel free to sign up today.
Sign up
yea, I have a block diagram. I'm drawing them on a daily basis :D lol

tried the post synthesis simulation, the file you sent me yesterday - the design works fine again.

So where are we Art ?

Did post synthesis simulations run ok ?

Is the FPGA functioning ok on the bench or do you still have wonky outputs ?


Was busy yesterday so was home late...hence no reply yesterday sorry about that m8.
 
Hi Mini, i was expecting that post synthesis would not run fine, but it did. I have a strange feeling that when i will check signals on scopes they will be wonky :)

Still working to make a proper pipeline and trying to find the problems of state machine.
 
If your Behavioural level RTl sims ok and the Post Synthesis simulaiton is ok then I'd suggest moving onto the post fit functional model then sicne your design is small enough you could try the Post fit timimg model...

The last one (post fit timimg model should be as close as possible as to the bench FPGA set up)

If after all these test benches your sims are Ok and you still have issues on the bench then I'd look at my FPGA input clock and the reset signal that you apply and then the Input signals....As something in your testbench is not lineing up with what you actually have on the bench.
 
for now only RTL looks fine, I've asked a lecturer in my college about the problem, and he suggested to use fast_output_registers when configuring pinout.

Well, what do you know, :) Finally i almost completed my new design with working pipeline, according to TB simulation, i went through post-synthesis - COMPLETE SILENCE - no signals! :(
After enabling fast_output_registers for my output signals, and running post-synthesis again, almost all of my output signals appeared in the simulation. With almost correct logic

But with strange glitches :( That's a BIG step in my design :D
 
it was a first time when i saw a big difference between the TB simulation, and post-synthesis simulation.
 
Question - when creating a gated clock, should I use MUX or simple AND gate will be fine? Or it doesn't matter at all?
 
GATED CLOCKs ! ! ! o_O (Big boys stuff ;) )

Is your logic that big that you have such a massive clock tree and need to use gated clocks ??

Passing clocks through regualr logic (simple gates, mux etc) is usually avoided if at all possible as you could now have some parts of your design being clocked at T and other parts at T+1ns for example.
Look in the altera manuals for some specific Altera primitives for clock managment. It should have special clock buffers, muxes etc...the muxes should be able to garauntee glitchless switching, low latency, high frequency of operation that sort of stuff.

Actually a quick serach and I found this for you ;) http://www.altera.com/literature/ug/ug_altclock.pdf

It gives the VHDL instantation for the block too near the back and also which libraries you need to include to be able to access it.

component altclkctrl
generic (
clock_type:string := "AUTO";
intended_device_family:string := "unused";
ena_register_mode:string := "falling edge";
implement_in_les:string := "OFF";
number_of_clocks:natural := 4;
use_glitch_free_switch_over_implementation:string := "OFF";
width_clkselect:natural := 2;
lpm_hint:string := "UNUSED";
lpm_type:string := "altclkctrl"
);
port(
clkselect:in std_logic_vector(width_clkselect-1 downto 0) :=
(others => '0');
ena: in std_logic := '1';
inclk: in std_logic_vector(number_of_clocks-1 downto 0) :=
(others => '0');
outclk:eek:ut std_logic
);
end component;


You'll need to include this lib in order to use the altclkctrl block

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;


Have a read of the .pdf document and see if it can be configured to fit the need you have.

Nice little page too on clock multiplexers TimeQuest Clock Multiplexer Examples

Its good to hear you are begining to see some differences between the RTL and post synthesis sims...At least if the post synth sims match what you see in real life on the fpga then you know if you fix it to work in sims then the real life design should be fixed now too ;)
 
I have 4 blocks that have to perform different operations but not simultaneously. To make them work in a specific order i just kill specific processes in those blocks by timing them with gated clock.
I know that joining clock with extra logic is avoided, but not always. (I guess)

this is how it has to be (according to my test bench) the only thing i generate is clock, and reset - and it continues from that point by itself
 

Attachments

  • des.jpg
    des.jpg
    92.7 KB · Views: 12
it's good i've turned off the porn sites in a background :D lol
 
can i use this ALTCLKCTRL component to take the CLOCK to the outer world, i mean - OFF the chip, to the output pin?
 
I'd say that would be ok art, usually if we bring clocks out of the chip for example if a clock is clocking an output databus off chip then all the output registers are clocked with the CLK but teh we invert the CLK as we bring it to the outside world.

This allows the CLKB to be then correctly aligned with the data bus for the next device down the line to use it to clock the data into himself.

CLK = regualr clock
CLKB = clock Bar or inverted clock

From the CCD are you getting the data on a line by line basis, it looks like you have a sync signal then a burst of data (i'm assuming each burst is a line)
 
Ok, thanks :)

Yea, i'm getting the data line by line :) but, for now i'm getting shit only, because half of it wasn't functioning in reality :D lol

It's a new design, that I've managed to build in these couple of days, it was working component by component in the lab (providing signals). Tomorrow i'll test it in the lab again, when all components are tied up together.
 
Nice job, slow and steady building these things up is the way. Code a block sim it...Next block, sim it....Join blocks together sim again ! !

If you are doing it right you should be getting sick of doing sims ;)
 
I am sick already :D lol

But I can't get rid of sims completely. At least for now.

Tried to work out the altclkctr, gave me a headache. If i need only 1 input only, ffs why they give me std_logic_vector of 4 inputs? I give up for today :D

enough is enough
 

Users who are viewing this thread